library IEEE;
use IEEE.std_logic_1164.all;

entity ctrlUnit is
  
  port (
    clk, reset       : in  std_logic;
    rd, wr           : in  std_logic;
    DRdy, FErr, OErr : in  std_logic;
    BufE, RegE       : in  std_logic;
    IntR             : out std_logic;
    IntT             : out std_logic;
    ctrlReg          : out std_logic_vector(7 downto 0));

end ctrlUnit;
